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ia 82050 data sheet asynchronous serial controller february 25, 2011 ia211030617 - 0 8 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 1 of 22 1 - 888 - 824 - 4184 ia82 050 asynchronous serial controller data sheet ? ?
ia 82050 data sheet asynchronous serial controller february 25, 2011 ia211030617 - 0 8 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 2 of 22 1 - 888 - 824 - 4184 copyright 2008 by innovasic semiconductor, inc. published by innovasic semiconductor, inc. 3737 princeton drive ne, suite 130, albuquerque, nm 87107 intel i s a registered trademark of intel corporation miles? is a trademark of innovasic semiconductor, inc. ?
ia 82050 data sheet asynchronous serial controller february 25, 2011 ia211030617 - 0 8 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 3 of 22 1 - 888 - 824 - 4184 table of contents list of figures ................................ ................................ ................................ ................................ .. 4 list of tables ................................ ................................ ................................ ................................ ... 4 1. features ................................ ................................ ................................ ................................ ... 5 2. description ................................ ................................ ................................ .............................. 7 3. functional overview ................................ ................................ ................................ .............. 9 3.1 transmitter ................................ ................................ ................................ .................... 9 3.2 receiver ................................ ................................ ................................ ......................... 9 3.3 bus interface ................................ ................................ ................................ ................. 9 3.4 register description ................................ ................................ ................................ .... 10 4. register descriptions ................................ ................................ ................................ ............ 11 4.1 baud rate generator a divide count, msb and lsb (bah/bal) .......................... 11 4.2 general interrupt enable register (ger) ................................ ................................ ... 11 4.3 general interrupt register (gir) ................................ ................................ ................ 11 4.4 line configure register (lcr) ................................ ................................ ................... 11 4.5 line status register (lsr) ................................ ................................ ......................... 12 4.6 modem control register (mcr) ................................ ................................ ................ 12 4.7 modem status register (msr) ................................ ................................ ................... 13 4.8 receive data register (rxdata) ................................ ................................ ............. 13 4.9 scratch register (scr) ................................ ................................ ............................... 13 4.10 transmit data register (txdata) ................................ ................................ ........... 14 5. ac/dc parameters ................................ ................................ ................................ ............... 15 6. dc characteristics ................................ ................................ ................................ ................ 16 7. ac characteristics ................................ ................................ ................................ ................ 17 8. packaging informat ion ................................ ................................ ................................ .......... 18 8.1 pdip package ................................ ................................ ................................ .............. 18 8.2 plcc package ................................ ................................ ................................ ............. 19 9. innovasic part number cross - reference ................................ ................................ .............. 20 10. revision history ................................ ................................ ................................ ................... 21 11. for additional information ................................ ................................ ................................ ... 22 ?
ia 82050 data sheet asynchronous serial controller february 25, 2011 ia211030617 - 0 8 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 4 of 22 1 - 888 - 824 - 4184 list of figures figure 1. package pinout ................................ ................................ ................................ ................ 6 figure 2. functional block diagram ................................ ................................ .............................. 8 figure 3. pdw physical package dimensions ................................ ................................ ............. 18 figure 4. plcc physical package dimensions ................................ ................................ ............ 19 list of table s table 1. register summary ................................ ................................ ................................ ........... 10 table 2. general interrupt enable register ................................ ................................ .................. 11 table 3. general interrupt register ................................ ................................ .............................. 11 table 4. line configure register ................................ ................................ ................................ .. 12 table 5. line status register ................................ ................................ ................................ ........ 12 table 6. modem control register ................................ ................................ ................................ 13 table 7. modem status register ................................ ................................ ................................ ... 13 table 8. ac/dc parameters ................................ ................................ ................................ ......... 15 table 9. dc characteristics ................................ ................................ ................................ .......... 16 table 10. ac charact eristics ................................ ................................ ................................ ........ 17 table 11. innovasic part number cross - reference for the pdip ................................ ................ 20 table 12. innovasic part number cross - reference fo r the plcc ................................ ............... 20 ?
ia 82050 data sheet asynchronous serial controller february 25, 2011 ia211030617 - 0 8 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 5 of 22 1 - 888 - 824 - 4184 1. features ? form, fit and function compatible with the intel 82050 ? packaging options available: 28 - pin plastic dip and 28 - lead plastic leaded chip carrier (see figure 1, package pinout) ? asynchronous serial cha nnel operation ? separate transmit and receive fifos with programmable threshold ? programmable baud rate generator up to 288k baud ? special protocol features C loopback modes C 5 - to 8 - bit character format the ia82050 is a "plug - and - play" drop - in replacement for t he original ic. innovasic produces replacement ics using its miles tm , or managed ic lifetime extension system, cloning technology. this technology produces replacement ics far more complex than "emulation" while ensuring they are compatible with the origi nal ic. miles tm captures the design of a clone so it can be produced even as silicon technology advances. miles tm also verifies the clone against the original ic so that even the "undocumented features" are duplicated. this data sheet documents all nece ssary engineering information about the ia82050 including functional and i/o descriptions, electrical characteristics and applicable timing. ?
ia 82050 data sheet asynchronous serial controller february 25, 2011 ia211030617 - 0 8 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 6 of 22 1 - 888 - 824 - 4184 figure 1 . package pinout ( 6 ) txd ( 1 ) d 4 ( 2 ) d 5 ( 3 ) d 6 ( 4 ) d 7 ( 5 ) int ( 7 ) vss ( 8 ) x 2 or out 2 n ( 9 ) x 1 or clk ( 10 ) sclk or rin ( 11 ) dsrn or ta or out 0 n ( 12 ) dcdn or iclk or out 1 n ( 13 ) rxd ( 14 ) ctsn ( 28 ) d 3 ( 27 ) d 2 ( 26 ) d 1 ( 25 ) d 0 ( 24 ) a 2 ( 23 ) a 1 ( 22 ) a 0 ( 21 ) vdd ( 20 ) rdn ( 19 ) wrn ( 18 ) csn ( 17 ) reset ( 16 ) rtsn ( 15 ) dtrn or tb ( 6 ) txd ( 5 ) int ( 7 ) vss ( 8 ) x 2 or out 2 n ( 9 ) x 1 or clk ( 10 ) sclk or rin ( 11 ) dsrn or ta or out 0 n ( 25 ) d 0 ( 24 ) a 2 ( 23 ) a 1 ( 22 ) a 0 ( 21 ) vdd ( 20 ) rdn ( 19 ) wrn ( 4 ) d 7 ( 3 ) d 6 ( 2 ) d 5 ( 1 ) d 4 ( 28 ) d 3 ( 27 ) d 2 ( 26 ) d 1 ( 18 ) c s n ( 17 ) r e s e t ( 16 ) r t s n ( 15 ) d t r n o r t b ( 14 ) c t s n ( 13 ) r x d ( 12 ) d c d n o r i c l k o r o u t 1 n 28 - pin dip ia 82050 28 - lead lcc ia 82050 ?
ia 82050 data sheet asynchronous serial controller february 25, 2011 ia211030617 - 0 8 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 7 of 22 1 - 888 - 824 - 4184 2. description the ia82050 is an asynchronous serial controll er that provides a cpu interface to one transmit and one receive channel. it is form, fit, and function compatible with the intel? 82050 and 82510. configuration registers are used to control the serial channel, interrupts, and modes of operation. the c pu controls this device via address and data lines with read/write control. the cpu also uses this interface to read and write data to receive and transmit data through the serial channel. fifos and various serial modes can be used to help off - load the c pu from transmitting and receiving data. an interrupt line provides an indication to the cpu that the device requires servicing. the device can be configured for 8250a/16450 compatibility. see figure 2, functional block diagram . ?
ia 82050 data sheet asynchronous serial con troller february 25, 2011 ia211030617 - 0 8 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 8 of 22 1 - 888 - 824 - 4184 figure 2 . functional block diagram ia82510 bus interface (reset logic, registers, interrupt generation, config., status, rxdata txdata timing (baud rate generators a & b, clocking pin configuration receiver transmitter modem txd rxd x2 or out2n sclk or rin x1 or clk rtsn ctsn dsrn or ta or out0n dcdn or iclk or out1n dtrn or tb a(2:0) d(7:0) rdn wrn csn int reset ?
ia 82050 data sheet as ynchronous serial controller february 25, 2011 ia211030617 - 0 8 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 9 of 22 1 - 888 - 824 - 4184 3. functional overview 3.1 transmitter the transmit function consists of a one - character fifo, and a transmit engine. the transmit engine is responsible for reading the data out of the fifo and placing it in the proper ord er on the txd pin. the transmit engine is highly configurable to be compatible with numerous formats, including 16450 and 8250 modes of communication. transmit communication parameters that can be programmed include: ? parity modes ? stop bits ? character leng th for more details, see chapter 5, register descriptions . 3.2 receiver the receiver function consists of a one - character fifo and a receive engine. the receive engine is responsible for sampling the data on the rxd i nput pin, formatting the data, and placing the data in the fifo. the receive engine is highly configurable with parameters that include: ? parity modes ? stop bits ? character length for more details, see chapter 5, regi ster descriptions . 3.3 bus interface the bus interface is a simple interface that allows a micro - processor or micro - controller to read and write the ia82050 registers. it consists of the following i/o lines: ? a0, a1, a2 : 3 - bit address ? d0 - d7 : 8 - bit data ? rdn: active low read enable ? wrn: active low write enable ? csn: active low chip select ? int: interrupt output ? reset: chip reset ?
ia 82050 data sheet as ynchronous serial controller february 25, 2011 ia211030617 - 0 8 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 10 of 22 1 - 888 - 824 - 4184 3.4 register description table 1 presents the register summary. table 1 . register summary register addr dlab mode default bah 001 1 r/w 00000000 bal 000 1 r/w 00000010 ger 001 0 r/w 00000000 gir 010 x r 00000001 lcr 011 x r/w 00000000 lsr 101 x r/w 01100000 mcr 100 x r/w 00000000 msr 110 x r/w 00000000 rxdata 000 0 r unknown scr 111 x r/w 00000000 txdata 00 0 0 w n/a ?
ia 82050 data sheet as ynchronous serial controller february 25, 2011 ia211030617 - 0 8 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 11 of 22 1 - 888 - 824 - 4184 4. register descriptions 4.1 baud rate generator a divide count, msb and lsb (bah/bal) baud rate generator a divide count (msb and lsb) C when generating txclk or rxclk, the selected source clock will be divided by this value (addr 001/000, mode r/w, default 00000000/00000010) . 4.2 general interrupt enable register (ger) enables the general categories of interrupts when generating int (addr 001, mode r/w, default 00000000) . table 2 . ge neral interrupt enable register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 mie rxie tfie rfie mie modem interrupt enable, 1=enabled, 0=disabled rxie receive interrupt enable, 1=enabled, 0=disabled tfie transmit fif0 interrupt enable, 1=enabled, 0=disabled rfie receive fifo interrupt enable, 1=enabled, 0=disabled 4.3 general interrupt register (gir) read - only interrupt register containing priority encoded enabled interrupt vector and interrupt pending flag. writes to this register only affect bank pointer bits (addr 010, mode r, default 00000001) . table 3 . general interrupt register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 bank1 bank0 0 0 bi1 bi0 ipn bank1, bank0 C bank pointer C not used in ia82050, user must ensure these bits are never written bi1, bi0 C interrupt vector 11=receive interrupt (highest priority) 10=receive fifo interrupt 01=transmit fif0 interrupt 00=modem interrupt (lowest priority) ipn C interrupt pending (1=no interrupt pending, 0=interrupt pending) 4.4 line configure register (lcr) defines configuration of serial message (addr 011, mode r/w, default 00000000) . ?
ia 82050 data sheet as ynchronous serial controller february 25, 2011 ia211030617 - 0 8 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 12 of 22 1 - 888 - 824 - 4184 table 4 . line configure register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dlab sbk pm2 pm1 pm0 sbl0 cl1 cl0 dlab C divisor latch access bit (see register summary table) sbk C set break (0=normal txd operation, 1=txd held low C break condition) pm2, pm1, pm0 C parity mode xx0=no parity 001=odd parity 011=even parity 101=high parity 111=low parity sbl0 C stop bit length 0 = 1 stop b it 1 = 2 stop cl1, cl0 C character length 00=5 bits 01=6 bits 10=7 bits 11=8 bits 4.5 line status register (lsr) reports status of serial link (compatible with 8250). bkd, fe, pe, and oe are cleared when read. writing a zero to rfir acknowledges th e interrupt (addr 101, mode r/w, default 01100000) . table 5 . line status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 txst tfst bkd fe pe oe rfir txst transmitter status (1=tx idle or disabled, 0=tx busy) tfst t ransmit fifo status (1=tx fifo empty, 0=full) bkd break detected (1=break detected, 0=no break detected) fe framing error (1=framing error, 0=no framing error) pe parity error (1=parity error, 0=no parity error) oe overrun error (1=overrun error, 0=no overrun error) rfir receive fifo interrupt request (1=rx fifo full, 0=empty) 4.6 modem control register (mcr) drives the general purpose outputs that may be used as modem control discretes. (addr 100, mode r/w;w, default 00000000) ?
ia 82050 data sheet as ynchronous serial controller february 25, 2011 ia211030617 - 0 8 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 13 of 22 1 - 888 - 824 - 4184 table 6 . modem control register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 lc out2 out1 rts dtr lc loopback control (0=normal operation, 1=loopback mode) out2 output 2 state (1=out2n low, 0=out2n high) out1 output 1 state (1=out1n low, 0=out 1n high) rts ready to send state (1=rtsn low, 0=rtsn high) dtr data terminal ready state (1=dtrn low, 0=dtrn high) 4.7 modem status register (msr) reports status of modem input pins dcdn, rin, dsrn and ctsn. all but ctsn must be enabled via the pmd regist er. the delta bits are cleared on a read. (addr 110, mode r/w;r, default 00000000) . table 7 . modem status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dcdc ric dsrc ctsc ddcd dri ddsr dcts dcdc dcdn complement (1= dcdn low, 0=dcdn high) ric rin complement (1=rin low, 0=rin high) dsrc dsrn complement (1=dsrn low, 0=dsrn high) ctsc ctsn complement (1=ctsn low, 0=ctsn high) ddcd delta dcdn (1=dcdn changed since last read, 0=no change) dri delta rin (1=rin transiti oned low since last read, 0=no change or transition high) ddsr delta dsrn (1=dsrn changed since last read, 0=no change) dcts delta ctsn (1=ctsn changed since last read, 0=no change) 4.8 receive data register (rxdata) (addr 000, mode r, default unknown) rec eive data - a read from this location removes the data receive byte from the rx fifo. the lsb of rxdata will correspond to the first bit received after the start bit of the serial character. the msb will correspond to the eighth data bit received after t he start bit. if the character length (lcr_cl) is less than eight, the unused rxdata bits will be zero. a read from rxdata will be directly from the rx fifo. 4.9 scratch register (scr) (addr 111, mode r/w, default 00000000) ?
ia 82050 data sheet as ynchronous serial controller february 25, 2011 ia211030617 - 0 8 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 14 of 22 1 - 888 - 824 - 4184 general purpose scratch pad registe r to be defined by user. 4.10 transmit data register (txdata) (addr 000, mode w, default n/a) transmit data - a write to this location adds a data byte to the tx fifo, and initiates the transmit sequence. ?
ia 82050 data sheet as ynchronous serial controller february 25, 2011 ia211030617 - 0 8 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 15 of 22 1 - 888 - 824 - 4184 5. ac/dc parameters table 8 . ac/d c parameters parameters absolute maximum ratings supply voltage, v dd - 0.3v to +6.0v input voltage, v in - 0.3v to v dd +0.3v input pin current, iin 10 ma, 25 c operating temperature range - 40 c to +85c ambient temperature under bias - 40c to +85c storage temperature - 55c to +150c lead temperature +300c, 10 sec. power dissipation 155 mw, 125c, 25mhz, 15% toggle caution: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. operating the device beyond the conditions indicated in the recommended operating conditions section is not recommended. operation at the absolute maximum ratings may adversely affect device reliability. the input and output parametric values in section vii - b, parts 1, 2 and 3, are directly related to ambient temperature and dc supply voltage. a temperature or supply voltage range other than those specified in the operating conditions above will affect these values, making invalidating innovasics guarantee of part performance. ?
ia 82050 data sheet as ynchronous serial controller february 25, 2011 ia211030617 - 0 8 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 16 of 22 1 - 888 - 824 - 4184 6. dc characteristics table 9 . dc cha racteristics symbol parameter notes min max unit v il input low voltage (1) - 0.5 0.3 v v ih1 input high voltage - cerdip (1) 2.1 v dd +.3 v v ih2 input high voltage - lcc (2) 2.1 v dd +.3 v v ol output low voltage (2),(8) 0.4 v v oh output high voltage (3),(8) 2. 4 v i li input leakage current (4) 1 a i lo 3 - state leakage current (5) 10 a i cc power supply current (6) 1.12 ma/mhz i pu strapping pullup resistor (12) - 28.3 - 137 a i stby standby supply current (9) 100 a i ohr rtsn, dtrn strapping current (1 0) 1.92 ma i olr rtsn, dtrn strapping current (11) n/a ma c in input capacitance (7) 5 pf c io i/o capacitance (7) 6 pf c xtal x1, x2 load 6 pf notes: 1. does not apply to clk/x1 pin, when configured as crystal oscillator input (x1). 2. @iol = 1.92 ma 3. @io h = 1.92 ma 4. 0< vin ia 82050 data sheet as ynchronous serial controller february 25, 2011 ia211030617 - 0 8 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 17 of 22 1 - 888 - 824 - 4184 7. ac characte ristics table 10 . ac characteristics parameter min max notes clk period 54 ns 250 ns divide by two clk period 54 ns 108 ns no divide by clk low time 25 ns clk high time 25 ns clk rise time 10 ns divide by two measured be tween 0.3 * vdd and 0.7 * vdd clk fall time 10 ns divide by two measured between 0.3 * vdd and 0.7 * vdd clk rise time 15 ns no divide by clk fall time 15 ns no divide by crystal frequency 1 mhz 20 mhz reset width 8 * clock period rts/dtr low s etup to reset inactive 6 * clock period rts/dtr low hold after reset inactive clock period C 20 ns rdn active width 2* clock period + 65 ns address/csn setup time to rdn active 7 ns address/csn hold after rdn inactive 0 ns rdn or wrn inactiv e to active delay clock period + 15 ns data out float delay after rdn inactive 40 ns wrn active width 2 * clock period + 15 ns address csn setup time to wrn active 7 ns address and csn hold time after wrn 0 ns data in setup time to wrn inact ive 90 ns data in hold time after wrn inactive 12 ns sclk period 216 ns 16x clocking mode sclk period 3500 ns 1x clocking mode rxd setup time to sclk high 250 ns rxd hold time after sclk high 250 ns txd valid after sclk low 170 ns txd de lay after rxd 170 ns remote loopback ?
ia 82050 data sheet as ynchronous serial controller february 25, 2011 ia211030617 - 0 8 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 18 of 22 1 - 888 - 824 - 4184 8. packaging information 8.1 pdip package figure 3 . pdw physical package dimensions legend: symbol 28 (in inches) min max a - 0 .200 a1 0 .015 - b 0 .015 0 .020 b1 0 .050 0 .070 c 0 .008 0 .012 e 0 .580 0 .610 e1 0 .520 0 .560 e 0 .100 typ ea 0 .580 - eb - 0 .686 l 0 .100 min b2 - - s - - d l a 1 a b b 1 e s i d e v i e w ( l e n g t h ) p i n i d e n t i f i e r 1 p i n c o u n t d i r e c t i o n e 1 e t o p e a e b c s i d e v i e w ( w i d t h ) ?
ia 82050 data sheet as ynchronous serial controller february 25, 2011 ia211030617 - 0 8 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 19 of 22 1 - 888 - 824 - 4184 8.2 plcc package legend: symbol 28 (in millimeters) min max a 4.20 4.57 a1 2.29 3.04 d1 11.43 11.58 d2 9.91 10.92 d3 7.62 bsc e1 11.43 11.58 e2 9.91 10.92 e3 7.62 bsc e 1.27 bsc d 12.32 12.57 e 12.32 12.57 figure 4 . plcc physical package dimensions ? d3 e3 pin 1 identifier & zone 1.22/1.07 2 plcs top view .10 .51 min. r 1.14 / .64 seating plane a1 e .81 / .66 a .53 / .33 d2 / e2 side view d d1 e e1 bottom view
ia 82050 data sheet as ynchronous serial controller february 25, 2011 ia211030617 - 0 8 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 20 of 22 1 - 888 - 824 - 4184 9. innovasic part number cross - reference table 11 . innovasic part number cross - reference for the pdip innovasic part number intel part number package type temperature grades ia82050 - pdw28i - r - 01 lead free ( rohs - compliant ) p82050 tp82050 28 - pin p last ic d ual i n - line p ackage (pdip) (600 mil s) industria l table 12 . innovasic part number cross - reference for the plcc innovasic part number intel part number package type temperature grades ia82050 - plc28i r2 lead free ( rohs - compliant) N82050 tN82050 28 - lead p lastic l eaded c hip c arr ier (plcc) industrial ?
ia 82050 data sheet as ynchronous serial controller february 25, 2011 ia211030617 - 0 8 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 21 of 22 1 - 888 - 824 - 4184 10. revision history the table below presents the sequence of revisions to document ia211 0 30617 . date revision description page(s) august 19, 2008 06 corrected control number and reformatted some elements to meet publication standard s. na october 15 , 2008 07 corrected part number on cover page , enlarged package pinout and functional block diagram figures, corrected trademark references (p. 2), changed pin to lead in lcc package pinout figure, changed lead to pin in pdip physi cal page dimensions figure and part number table, formatted part cross - reference table to meet publication standards, added for additional information chapter . 1, 5, 6, 17, 18 , 20 february 25, 2011 08 removed packaging options to support the eliminatio n of snpb lead plating options . 20 ?
ia 82050 data sheet as ynchronous serial controller february 25, 2011 ia211030617 - 0 8 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 22 of 22 1 - 888 - 824 - 4184 11. for additional information the ia82050 is a "plug - and - play" drop - in replacement for the original ic. this data sheet documents all necessary engineering information about the ia82050 including functional and i/o descrip tions, electrical characteristics and applicable timing. the innovasic support team wants our information to be complete, accurate, useful, and easy to understand. please feel free to contact our experts at innovasic at any time with suggestions, comments , or questions. innovasic support team 3737 princeton ne suite 130 albuquerque, nm 87107 (505) 883 - 5263 fax: (505) 883 - 5477 toll free: (888) 824 - 4184 e - mail: support@innovasic.com website: www.innovasic.com ?

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